1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for dividing capacitor electrodes of a FEC (Floating Electrode Capacitor) type memory cell which is useful as a DRAM (Dynamic Random Access Memory) cell having a wiring width of 0.8.mu.m or less such as a 16 MDRAM.
2. Description of the Prior Art
FIGS. 6 and 7 show electric equivalent circuits of a FEC type DRAM cell and a conventional DRAM cell, respectively.
Referring to the FEC type DRAM cell, a capacitor 61 is connected to transistors 62 and 63. If four kinds of potentials are applied to lower and upper electrodes 61a and 61b of the capacitor 61 as shown in Table 1, the information for 2 bits can be stored by the capacitor 61 and transistors 62 and 63 shown in FIG. 6.
TABLE 1 ______________________________________ Applied potential of a FEC type DRAM cell State Upper electrode Lower electrode ______________________________________ "0" Vcc 0 "1" (2/3) Vcc (1/3) Vcc "2" (1/3) Vcc (2/3) Vcc "3" 0 Vcc ______________________________________
Referring to the conventional memory cell shown in FIG. 7, capacitor electrodes comprises storage electrodes 31 and plate electrodes 32. The storage electrodes 31 are electrically insulated from each other per memory cell. The plate electrodes 32 are not electrically connected to each other and serve as fixed potentials of (1/2) Vcc. The storage electrodes 31 are formed by etching an electrode material such as polysilicon and dividing the same per memory cell. The plate electrodes 32 are common electrodes. Consequently, it is not necessary to divide the plate electrodes 32 per memory cell. In the FEC type memory cell, it is necessary to electrically divide both electrodes of the capacitor in similar to the storage electrodes 31 of the conventional memory cell. The requirements of capacitor formation are different. Accordingly, a method for forming the capacitor of the conventional DRAM cell is not suitable for forming the capacitor of the FEC type DRAM cell for the following reasons.
FIGS. 8 and 9 are plan views of the electrodes of a memory capacitor which is formed in a capacitor formation step of the conventional method. FIG. 8 shows the capacitor of the conventional DRAM cell. FIG. 9 shows the capacitor of the FEC type DRAM cell.
Referring to the conventional memory cell, the plate electrodes 32 (shown in oblique lines in FIG. 8) are not divided between adjacent cells 41 and 41. Consequently, even if the plate electrodes 32 are shifted from the storage electrodes 31, an overlapping amount of the electrodes 31 and 32 of the capacitor is not greatly changed. Thus, the capacity of the capacitor is seldom increased or decreased. A work line is indicated at 42.
Referring to the FEC type DRAM cell shown in FIG. 9, when the capacitor electrode comprising the lower and upper electrodes 61a and 61b are shifted, the overlapping amount of electrodes 61a and 61b is reduced so that the capacity is decreased. Consequently, it is necessary to ensure the excessive storage capacity of the memory cell correspondingly to the decrease in capacity caused by shift. Accordingly, there is reduced by half the advantage that the same amount of information can be stored by means of half of the capacitors. A word line is indicated at 91. A local wiring is indicated at 64.
To make the most of the advantage of the FEC type DRAM cell, it is necessary to employ a method for forming a capacitor wherein the capacity is not decreased even if the electrodes are shifted at the time of processing.
It is an object of the present invention to provide a method for forming a capacitor suitable for the FEC type DRAM cell.